1. Field of the Invention
The present invention relates to a method for forming a storage node of a capacitor, and more particularly to a method for forming a storage node of a capacitor directly connected to an underlying conductive region.
2. Description of the Related Art
As the information society rapidly develops, semiconductor devices are required to have rapid processing speed for handling much information. Thus, cells should be highly integrated in one chip. There have been many efforts to reduce the design rule of the semiconductor in order to integrate a number of cells in one semiconductor device.
In accordance with the increasing integration of the semiconductor device, the metal wiring of the semiconductor device is formed using tungsten so as to improve the operation speed of the semiconductor device. However, an oxide film may be abnormally grown on the tungsten metal wiring due to its intrinsic properties during the thermal process for manufacturing the semiconductor device.
FIG. 1A is a cross-sectional picture showing the bit line including tungsten obtained by a scanning electron microscope (SEM).
As shown in FIG. 1A, an oxide film is abnormally grown on a region 100 of a bit line toward a sidewall of the bit line. When the metal wiring having the abnormally grown oxide film is exposed in the adjacent open region so that the metal wiring is used as an electrical passage, a failure such as an electrical short is caused.
A spacer is additionally formed on the sidewall of the bit line to overcome the above-mentioned problem, however, the cost for manufacturing the semiconductor device may increase due to the formation of the spacer.
As for a dynamic random access memory (DRAM) having cell elements such as a transistor and a capacitor, the area for forming the cell elements should be reduced in order to fabricate a highly integrated DRAM. Though the capacitor is formed in the diminished area, the storage capacitance of the capacitor should be sufficiently maintained because the capacitor should have an adequate data storage capacity to operate as a data storage element.
When the size of the memory cell is reduced in accordance with the high integration of the semiconductor device, the size of the capacitor also decreases. Thus, the storage capacitance of the capacitor may be reduced. Hence, the storage node of the memory cell capacitor should have a wider surface area to store as much charge that is needed to maintain a desired storage capacitance. As a result, a capacitor having a three-dimensional structure like a cylinder has been developed to ensure sufficient storage capacitance by increasing the surface area of the storage node. When the height of the storage node increases in order to have a wider surface area, the aspect ratio of the storage node also increases, thereby deteriorating the structural stability of the storage node and causing the storage node to fall down.
Referring to FIG. 1B, a bridge 120 is generated by contacts between adjacent storage nodes due to a toppled storage node. The bridge 120 can cause the failure such as the electric short, so the wrong operation of the semiconductor device may occur. In addition, the performance of the semiconductor device may deteriorate because the contacting area between the storage node and an underlying contact region or a conductive pattern becomes narrower. Furthermore, when a contact is formed to electrically connect a storage node with an underlying conductive region or a conductive pattern, the resistance in the interface between the contact and the underlying conductive region or the conductive pattern may increase, so that the performance of the semiconductor device may further deteriorate.
To reduce the resistance in the interface in a contact region, there is provided a method for forming the storage node into the contact region as disclosed in U.S. Pat. No. 6,342,419. According to the above-mentioned method, however, a wet etching process is excessively performed to form an opening for forming a storage node pattern in order to increase the capacitance of the capacitor. Thus, according to the reduction of the design rule, adjacent patterns may make contact with each other to cause the electrical short. Also, the storage node pattern formed by the wet etching process may have an increasingly unstable structure as the height of the storage node pattern increases.